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NanoAmp Solutions, Inc. 1982 Zanker Road, San Jose, CA 95112 ph: 408-573-8878, FAX: 408-573-8877 www.nanoamp.com
N32T1630C1E
32Mb Ultra-Low Power Asynchronous CMOS PSRAM
2M x 16 bit Overview
The N32T1630C1E is an integrated memory device containing a 32 Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 2,097,152 words by 16 bits. It is designed to be identical in operation and interface to standard 6T SRAMS. The device is designed for low standby and operating current and includes a power-down feature to automatically enter standby mode. Also included are several other power saving modes: a deep sleep mode where data is not retained in the array and partial array refresh mode where data is retained in a portion of the array. Both these modes reduce standby current drain. The device can operate over a very wide temperature range of -25oC to +85oC.
Features
* Dual voltage for Optimum Performance: Vccq - 2.7V to 3.3V Vcc - 2.7V to 3.3V * Fast Cycle Times TACC < 60 nS TACC < 70 nS * Very low standby current ISB < 120A * Very low operating current Icc < 25mA * Dual rail operation VCCQ and VSSQ for separate I/O power rail * Compact Space Saving BGA Package
Product Family
Part Number Package Type Operating Temperature Power Supply 2.7V - 3.3V(VCC) Speed Standby Operating Current (ISB), Current (Icc), Max Max 120 A 3 mA @ 1MHz
N32T1630C1EZ
48-BGA
-25oC to +85oC
60ns 70ns
Figure 1: Pin Configuration
1 A B C D E F G H
LB I/O8 I/O9
2
OE UB I/O10
3
A0 A3 A5 A17 NC A14 A12 A9
4
A1 A4 A6 A7 A16 A15 A13 A10
5
A2 CE I/O1 I/O3 I/O4 I/O5 WE A11
6
ZZ I/O0 I/O2 VCC VSS I/O6 I/O7 A20
Table 1: Pin Descriptions
Pin Name A0-A20 WE CE ZZ OE LB UB I/O0-I/O15 VCC VSS VCCQ VSSQ Pin Function Address Inputs Write Enable Input Chip Enable Input Deep Sleep Input Output Enable Input Lower Byte Enable Input Upper Byte Enable Input Data Inputs/Outputs Power Ground Power I/O only Ground I/O only
VSSQ I/O11 VCCQ I/O12 I/O14 I/O13 I/O15 A18 A19 A8
48 Pin BGA (top) 6 x 8 mm
(DOC # 14-02-006 Rev C ECN 01-1040 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
1
NanoAmp Solutions, Inc. Functional Block Diagram
N32T1630C1E
Address Inputs A0 - A20
Address Decode Logic
2048K x 16 Memory Array
Input/ Output Mux I/O0 - I/O7 and Buffers I/O8 - I/O15
CE WE OE UB LB
Control Logic
ZZ
Functional Description
CE H X L L L H WE X X L H H X OE X X X3 L H X UB/LB X H L1 L L
1 1
ZZ H H H H H L
I/O1 High Z High Z Data In Data Out High Z High Z
MODE Standby2 Standby2 Write3 Read Output Disabled Low Power Modes
POWER Standby Standby Active Active Active Low Power
X
1. When UB and LB are in select mode (low), I/O0 - I/O15 are affected as shown. When LB only is in the select mode only I/O0 - IO7 are affected as shown. When UB is in the select mode only I/O8 - I/O15 are affected as shown. If both UB and LB are in the deselect mode (high), the chip is in a standby mode regardless of the state of CE. 2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally isolated from any external influence and disabled from exerting any influence externally. 3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.
Capacitance1
Item Input Capacitance I/O Capacitance Symbol CIN CI/O Test Condition VIN = 0V, f = 1 MHz, TA = 25oC VIN = 0V, f = 1 MHz, TA = 25oC Min Max 8 8 Unit pF pF
1. These parameters are verified in device characterization and are not 100% tested
(DOC # 14-02-006 Rev C ECN 01-1040 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
2
NanoAmp Solutions, Inc.
N32T1630C1E
Absolute Maximum Ratings1
Item Voltage on any pin relative to VSS Voltage on VCC Supply Relative to VSS Power Dissipation Storage Temperature Operating Temperature Symbol VIN,OUT VCC PD TSTG TA Rating -0.2 to VCC+0.3 -0.2 to 3.6 1 -65 to 125 -25 to +85 Unit V V W
o
C
oC
1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Operating Characteristics (Over Specified Temperature Range)
Item Supply Voltage Supply Voltage for I/O Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Output Leakage Current Read/Write Operating Supply Current @ 1 s Cycle Time2 Read/Write Operating Supply Current @ Min Cycle Time2 Standby Current Symbol VCC VCCQ VIH VIL VOH VOL ILI ILO ICC1 ICC2 ISB IOH = -0.5mA IOL = 0.5mA VIN = 0 to VCC OE = VIH or Chip Disabled VCC=VCCMAX, VIN=VIH / VIL Chip Enabled, IOUT = 0 VCC=VCCMAX, VIN=VIH / VIL Chip Enabled, IOUT = 0 Chip deselected, CE>VCC0.2, ZZ>VCC-0.2 and VIN = 0 or VCC -1 -1 Comments Min. 2.7 2.7 0.8VCCQ -0.2 0.8VCCQ 0.2VCCQ 1 1 3 25 120 Typ1 3.0 3.0 Max. 3.3 3.3 VCC+0.2 0.2VCCQ Unit V V V V V V A A mA mA A
1. Typical values are measured at Vcc=Vcc Typ., TA=25C and not 100% tested. 2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive output capacitance expected in the actual system.
(DOC # 14-02-006 Rev C ECN 01-1040 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
3
NanoAmp Solutions, Inc. Timing Test Conditions
Item Input Pulse Level Input Rise and Fall Time Input and Output Timing Reference Levels Operating Temperature
N32T1630C1E
0.1VCC to 0.9 VCC 5ns 0.5 VCC -25 oC to +85 oC
Output Load Circuit
I/O 50 pF Output Load
Power Up Sequence
After applying power, maintain a stable power supply for a minimum of 200us after CE > VIH.
(DOC # 14-02-006 Rev C ECN 01-1040 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
4
NanoAmp Solutions, Inc. Timings
Item Read Cycle Time Address Access Time Page Mode Read Cycle Time Page Mode Access Time Chip Enable to Valid Output Output Enable to Valid Output Byte Select to Valid Output Chip Enable to Low-Z output Output Enable to Low-Z Output Byte Select to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Byte Select Disable to High-Z Output Output Hold from Address Change Write Cycle Time Page Mode Write Cycle Time Chip Enable to End of Write Address Valid to End of Write Byte Select to End of Write Write Pulse Width Write Recovery Time Write to High-Z Output Address Setup Time Data to Write Time Overlap Data Hold from Write Time End Write to Low-Z Output Maximum Page Mode Cycle Chip Enable High Pulse Width Symbol tRC tAA tPC tPA tCO tOE tLB, tUB tLZ tOLZ tBZ tHZ tOHZ tBHZ tOH tWC tPWC tCW tAW tBW tWP tWR tWHZ tAS tDW tDH tOW tPGMAX tCP 10 0 20 0 5 10 5 10 0 0 0 5 60 25 50 50 50 50 0 5 5 5 5 25 -60 Min. 60
N32T1630C1E
-70 Max. Min. 70 25 Max. 20000 70 20000 25 70 25 70 10 5 10 0 0 0 5 5 5 5
Units
20000 60 20000 25 60 25 60
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
20000 20000
70 25 60 60 60 50 0
20000 20000
ns ns ns ns ns ns ns
5 0 20 0 5
ns ns ns ns ns
20000 10
20000
ns ns
Do not access device with invalid cycle time (shorter than tRC, tWC) for a continous period > 20us.
(DOC # 14-02-006 Rev C ECN 01-1040 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
5
NanoAmp Solutions, Inc. Timing of Read Cycle (CE = OE = VIL, WE = ZZ = VIH)
tRC Address tAA tOH
N32T1630C1E
Data Out
Previous Data Valid
Data Valid
Timing Waveform of Read Cycle (WE = ZZ = VIH)
tRC Address
tAA
CE tCO tLZ tOE OE tOLZ tLB, tUB LB, UB tBLZ Data Out High-Z tBHZ Data Valid tOHZ
tHZ
(DOC # 14-02-006 Rev C ECN 01-1040 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
6
NanoAmp Solutions, Inc. Timing Waveform of Page Mode Read Cycle (WE = ZZ = VIH)
tPGMAX Page Address (A4 - A20) tRC tPC
N32T1630C1E
Word Address (A0 - A3) tAA CE
tPA
tHZ
tCO tOE OE tOLZ LB, UB tLB, tUB tBHZ tOHZ
Data Out
High-Z
tBLZ,
(DOC # 14-02-006 Rev C ECN 01-1040 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
7
NanoAmp Solutions, Inc. Timing Waveform of Write Cycle (WE control, ZZ = VIH)
tWC Address tAW CE tCW tBW LB, UB
N32T1630C1E
tWR
tAS WE
tWP
tDW High-Z Data In tWHZ Data Out High-Z
tDH
Data Valid tOW
Timing Waveform of Write Cycle (CE Control, ZZ = VIH)
tWC Address tAW CE tAS tBW LB, UB tWP WE tDW Data In tWHZ Data Out High-Z tDH tWR tCW
Data Valid
(DOC # 14-02-006 Rev C ECN 01-1040 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
8
NanoAmp Solutions, Inc. Timing Waveform of Page Mode Write Cycle (ZZ = VIH)
tPGMAX Page Address (A4 - A20) tWC Word Address (A0 - A3) tAS tCW tPWC
N32T1630C1E
CE
tWP WE tLBW, tUBW LB, UB tDW High-Z tDH tPDW tPDH tPDW tPDH
Data Out
(DOC # 14-02-006 Rev C ECN 01-1040 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
9
NanoAmp Solutions, Inc.
N32T1630C1E
Power Savings Modes
The three low power modes are: * Reduced Memory Size * Partial Array Refresh * Deep Sleep Mode
The operation of the power saving modes is controlled by setting the Variable Address Register (VAR). This VAR is shown in the following "Variable Address Register" figure and is used to enable/disable the various low power modes. The VAR is set by using the timings defined in the figure titled "Variable Address Register (VAR) Update Timings". The register must be set in less then 1us after ZZ is enabled low.
1) Reduced Memory Size (RMS)
In this mode of operation, the 32Mb PSRAM can be operated as a 8Mb or 16Mb device. The mode and array size are determined by the settings in the VA register. The VA register is set according to the following timings and the bit settings in the table "Address Patterns for RMS". The RMS mode is enabled at the time of ZZ transitioning high and the mode remains active until the register is updated. To return to the full 32Mb address space, the VA register must be reset using the previously defined procedures. While operating in the RMS mode, the unselected portion of the array may not be used.
2) Partial Array Refresh (PAR)
In this mode of operation, the internal refresh operation can be restricted to a 8Mb or 16Mb portion of the array. The mode and array partition to be refreshed are determined by the settings in the VA register. The VA register is set according to the following timings and the bit settings in the table "Address Patterns for PAR". In this mode, when ZZ is active low, only the portion of the array that is set in the register is refreshed. The operating mode is only available during standby time (ZZ low) and once ZZ is returned high, the device resumes full array refresh. All future PAR cycles will use the contents of the VA register that has been previously set. To change the address space of the PAR mode, the VA register must be reset using the previously defined procedures.
3) Deep Sleep Mode
In this mode of operation, the internal refresh is turned off and all data integrity of the array is lost. Deep Sleep is entered by bringing ZZ low with the A4 register programmed to "Deep Sleep Enabled". The device will remain in this mode as long as ZZ remains low and when ZZ is driven high, all register settings will return to default states.
(DOC # 14-02-006 Rev C ECN 01-1040 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
10
NanoAmp Solutions, Inc. Variable Address Register A20 - A5 A4 A3
Array mode for ZZ Reserved for future Preferably set to all 0 0 = PAR mode (default) 1 = RMS mode 1 1 0 0
N32T1630C1E
A2
A1
A0
Array section 1 = 1/4 array 0 = 1/2 array 1 = Reserved 0 = Full array (default)
ZZ Enable/Disable 0 = Deep Sleep Enabled 1 = Deep Sleep Disabled (default) Array half
0 = Bottom array (default) 1 = Top array
Variable Address Register (VAR) Update Timings
tWC A0-A4 CE tAS WE ZZ LB, UB tZZWE tBW tAW tWP tWR
Deep Sleep Mode - Entry/Exit Timings
tWC A4 tAS CE tWP WE LB, UB ZZ tZZWE tBW tZZMIN tR tAW tWR
(DOC # 14-02-006 Rev C ECN 01-1040 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
11
NanoAmp Solutions, Inc.
N32T1630C1E
VAR Update and Deep Sleep Timings
Item ZZ low to WE low Deep Sleep Mode Deep Sleep Recovery Symbol tZZWE tZZMIN tR 10 200 Min Max 1 Unit us us us
Address Patterns for PAR (A3 = 0, A4 = 1)
A2 A1 A0 Active Section Address space Size Density
0 0 x 1 1
1 1 0 1 1
1 0 0 1 0
One-quarter of die One-half of die Full die One-quarter of die One-half of die
000000h - 07FFFFh 000000h - 0FFFFFh 000000h - 1FFFFFh 180000h - 1FFFFFh 100000h - 1FFFFFh
512Kb x 16 1Mb x 16 2Mb x 16 512Kb x 16 1Mb x 16
8Mb 16Mb 32Mb 8Mb 16Mb
Address Patterns for RMS (A3 = 1, A4 = 1)
A2 A1 A0 Active Section Address space Size Density
0 0 1 1
1 1 1 1
1 0 1 0
One-quarter of die One-half of die One-quarter of die One-half of die
000000h - 07FFFFh 000000h - 0FFFFFh 180000h - 1FFFFFh 100000h - 1FFFFFh
512Kb x 16 1Mb x 16 512Kb x 16 1Mb x 16
8Mb 16Mb 8Mb 16Mb
Low Power ICC Characteristics Item PAR Mode Standby Current RMS Mode Standby Current Deep Sleep Current Symbol
IPAR IRMSSB IZZ
Test
VIN = VCC or 0V, Chip Disabled, tA= 85oC VIN = VCC or 0V, Chip Disabled, tA= 85oC VIN = VCC or 0V, Chip in ZZ mode, tA= 85oC
Array Partition 1/4 Array 1/2 Array 4Mb Device 8Mb Device
Typ
Max 75 90 75 90 10
Unit uA uA uA
(DOC # 14-02-006 Rev C ECN 01-1040 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
12
NanoAmp Solutions, Inc. Figure 2: Ball Grid Array Package
A1 BALL PAD CORNER (3) D 0.230.05 0.900.10
N32T1630C1E
1. 0.300.05 DIA. E 2. SEATING PLANE - Z 0.15 Z 0.08 TOP VIEW SIDE VIEW 1. DIMENSION IS MEASURED AT THE A1 BALL PAD MAXIMUM SOLDER BALL DIAMETER. CORNER PARALLEL TO PRIMARY Z. 2. PRIMARY DATUM Z AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 3. A1 BALL PAD CORNER I.D. TO BE MARKED BY INK. K TYP J TYP e Z
SD
e SE
BOTTOM VIEW
Table 2: Dimensions (mm)
e = 0.75 D 60.10 E SD 80.10 0.375 SE 0.375 J 1.125 K 1.375 BALL MATRIX TYPE FULL
(DOC # 14-02-006 Rev C ECN 01-1040 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
13
NanoAmp Solutions, Inc. Ordering Information
N32T1630C1E
N32T1630C1EZ - XX I
60 = 60ns
Performance
70 = 70ns Z = BGA
Package
Revision History
Revision
A B C
Date
Feb 2004 Mar 2004 December 2004
Change Description
Initial Advance Release Package Datasheet Multiple Changes. Change ISB to 120uA. Added tCP timing parameter. Changed load circuit to 50pF and clarified low power mode with CE# high
(c) 2004 Nanoamp Solutions, Inc. All rights reserved. NanoAmp Solutions, Inc. ("NanoAmp") reserves the right to change or modify the information contained in this data sheet and the products described therein, without prior notice. NanoAmp does not convey any license under its patent rights nor the rights of others. Charts, drawings and schedules contained in this data sheet are provided for illustration purposes only and they vary depending upon specific applications. NanoAmp makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does NanoAmp assume any liability arising out of the application or use of any product or circuit described herein. NanoAmp does not authorize use of its products as critical components in any application in which the failure of the NanoAmp product may be expected to result in significant injury or death, including life support systems and critical medical instrument.
(DOC # 14-02-006 Rev C ECN 01-1040 The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
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